The present invention relates to hardware design and simulation and in particular, it relates to the design of hardware macros and arrays specifically. In particular it relates to a method for analyzing the macro schematic and the cross-section of a respective macro.
Large scale integrated circuits (LSI) or very large scale integrated circuits (VLSI) are current state-of-the-art hardware components. In order to develop such hardware components which are operated with clock rates of more than one Gigahertz the timing behavior of such components must be analyzed already in early stages of hardware development. The component is divided in manageable objects, so called macros. These macros are characterized by a macro specific timing specification. Macros are assumed in here to include both, logic and array-type switching structures.
In prior art, pre-product hardware, so called testsites, are usually developed, for example an array design. The simulation of this kind of macro is then verified and adjusted according to the hardware results to make sure that the signal propagation time within the wires and electric elements, for example transistors are adapted to the intended function of the respective logic macro or array circuit. This step includes the observation and control of race conditions.
In particular, when designing a hardware macro, i.e. a complex agglomeration of highly integrated logic circuits, in prior art usually a so-called schematic is generated which reflects part of the logical structure of the macro. Further, a so-called layout of the macro is generated which represents the physical structure of it. Both correspond to each other.
The straight forward approach in hardware simulation would now be to run a simulation which comprises the whole schematic of the macro. In spite of the above mentioned requirements regarding signal propagation time and in general the run-time behavior of the macro, any wire element must be included into this intended simulation. Further, any switching element, any load switched in parallel to one selected electrical path to be simulated is required to be included in said “ideal simulation”. This requirement, however, can not be met because there are far too many physical elements to simulate, which can not be handled by current timing simulation tools.
Thus, in prior art, so-called cross-sections are generated which represent a typical electrical path, for example, from an input pin of a macro to an output pin of the macro. Thus, such a cross-section represents only a specific part of the macro which is currently of interest, for example one bit of a 64 bit data path. This basic cross-section oriented approach helps to reduce the memory requirements and the required run time for a later simulation of the cross-section. The cross-section in turn comprises the above mentioned loads switched in parallel to the selected electrical path.
An independent model of the macro to be analyzed is thus introduced in prior art with the so called cross-section. Hereby, a problem arises which is the verification of said cross-sections against the full macro logic description, herein referred to as schematic. This problem is tried to be solved in prior art by producing a small, number of hardware chips implementing the hardware according to the given schematic, and measuring the run-time behavior along different electrical paths in the macro and comparing the measured data with the simulation results obtained by simulating one or more of the cross-sections representing the macro. This approach, however, has the disadvantage that hardware development is slow and expensive and thus not efficient.
Thus, it is desirable to have a reliable verification of a given cross-section or of a plurality of them against the full logic description comprised of the schematic. This desire is even increased in recent years since the increasing chip cache sizes and rising clock frequencies have urged the need for verification of the cross-sections even more, because the narrowing allowable technical tolerances increase the risk of circuit failures accordingly.